发明名称 TIME REDUCTION MECHANISM IN SCHEMATIC DESIGN ENTRY PAGE SETUP
摘要 A method and system for schematic design entry page setup are provided. In one aspect, the method may comprise presenting a user interface for entering information associated with a page layout for designing hardware logic schematics, retrieving the entered information and creating a specified number of pages for schematic design entry to automatically include the entered information on the pages. A system in one aspect may comprise a script operable to execute on a machine to present a user interface for entering information associated with a page layout for designing hardware logic schematics, the script further operable to retrieve the entered information. The system may also include means for creating a specified number of pages for schematic design entry to automatically include the entered information on the pages. An option to change and/or update information upfront without having to navigate to individual pages may be provided.
申请公布号 US2008172604(A1) 申请公布日期 2008.07.17
申请号 US20060617602 申请日期 2006.12.28
申请人 INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 SETHURAMAN SARAVANAN
分类号 G06F17/00;G06F17/50 主分类号 G06F17/00
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