| 摘要 |
PROBLEM TO BE SOLVED: To optimize a testing condition for delay fault diagnosis to set the reasonable number of fails.SOLUTION: A fault diagnosis system according to one embodiment, includes a control section that executes a plurality of tests for an integrated circuit, while changing testing conditions and controls a test apparatus to sample a fail log. A creation section creates a test result map from the fail log. An extraction section performs route tracking from a fail flip-flop in the fail log to acquire primary failure candidates. An analysis section calculates a delay and a timing margin of the fail flip-flop in the fail log by a simulation. A calculation section calculates, for all the primary fail candidates, a degree of coincidence between the timing margin of the simulation result and the test result map. An output section outputs a candidate with a highest degree of coincidence as the failure candidate.SELECTED DRAWING: Figure 1 |
