VERTICAL TRANSISTOR FOR RESISTIVE MEMORY

摘要

The present disclosure relates to a method of making a memory on semiconductor substrate, comprising: at least one data line, at least one selection line, at least one reference line, at least one memory cell comprising a select transistor having a control gate connected to the selection line, a first conduction terminal connected to a variable impedance element, the select transistor and the variable impedance element coupling the reference line to the data line, the select transistor comprising an embedded vertical gate produced in a trench formed in the substrate, and a channel region opposite a first face of the trench, between a first deep doped region and a second doped region on the surface of the substrate coupled to the variable impedance element.

主权项

1. A method, comprising:
manufacturing an integrated circuit including a memory with a memory cell, the manufacturing including: implanting deep down in a semiconductor substrate a first doped region, producing a trench in the substrate, from an upper face of the substrate, and which reaches the first doped region, producing an embedded gate in the trench, implanting on a first side of the trench, adjacent to the upper face of the substrate, a second doped region that forms a first conduction region of a select transistor having a gate that is the embedded gate and having a second conduction region that is the first doped region, and forming a variable impedance element electrically coupled to the second doped region.