| 摘要 |
An interface between a microprocessor uP or a local bus LB and a user-defined macro-cell is provided by two distributed modules, DMI MAIN and DMI PERIPHERAL. The DMI MAIN module is connected to the microprocessor bus or local bus at one side, and to an internal bus (labelled as COMMON BUS) at the other side. Each macro-cell is connected via point-to-point buses to a DMI PERIPHERAL module to transfer signals to and from the macro-cell. Each DMI PERIPHERAL module contains a set of peripheral resources such as registers and memories, including FIFO type memories. The DMI PERIPHERAL module is controlled by the DMI MAIN module for the execution of read/write commands from the microprocessor uP. The DMI PERIPHERAL modules are easily configurable to the specific needs of each macro-cell, thus making the interface adaptable. A protocol for operating such an interface is also disclosed. The interface may find particular use in ASIC (application specific integrated circuit) or FPGA (field programmable gate array) applications. |
