REDUCED EXTERNAL RESISTANCE FINFET DEVICE

摘要

The present invention relates generally to semiconductor devices, and more particularly, to a structure and method of reducing external resistance within fin field effect transistor (finFET) devices. A first spacer and a second spacer may be formed adjacent to a gate which may reduce capacitance in a substantial portion of a epitaxial source-drain region while also permitting a portion of the epitaxial source-drain region to be located close to a channel. By reducing capacitance from the gate on the substantial portion of the epitaxial source-drain region, resistance in the epitaxial source-drain region may be reduced which may result in increased device performance.

主权项

1. A method comprising:
forming an epitaxial source-drain region around a fin, the epitaxial source-drain region having a first epitaxial layer adjacent to and contacting a sidewall of a first spacer and below a second spacer and a second epitaxial layer on the first epitaxial layer adjacent to and contacting a sidewall of the second spacer, wherein the first spacer is adjacent to and contacting a sidewall of a gate, wherein the second epitaxial layer is formed on an upper surface of a substrate and around the first epitaxial layer.