System and method of fast phase aligned local generation of clocks on multiple FPGA system

摘要

An apparatus and method for fast phase aligned local generation of design clocks on a multiple FPGA system via clock generator replication is described. The apparatus includes a reference clock that generates a clock signal have a reference frequency and a plurality of programmable logic devices. Each programmable logic device includes phase locked loop circuitry that receives the clock signal from the reference clock and generates a local reference clock signal having a frequency based on the reference frequency and a clock generator that receives the local reference clock signal and generates local design clocks based on the local reference clock signal. Because each local design clock generator is synchronized by the same reference clock over a low skew line, the edges of the local design clocks are aligned.

主权项

1. A prototyping apparatus comprising:
a reference clock that generates a clock signal have a reference frequency; a plurality of programmable logic devices, where each of the plurality of programmable logic devices includes an aligned edge clock generator programmed therein that receives the reference clock and generates an internally generated local reference clock signal, each of the programmable logic devices having a partial user logic design programmed therein, the internally generated local reference clock signal drives a plurality of internally generated local design clock signals that are formed based on the internally generated local reference clock signal, the plurality of internally generated local design clock signals for each of the plurality of programmable logic devices being input to the partial user logic design programmed on respective ones of the plurality of programmable logic devices, wherein respective edges of each the internally generated local design clock signals generated by the clock generator of each programmable logic device are aligned, and wherein an operation cycle of the user design logic programmed into respective ones of the plurality of logic devices is scheduled for each edge of a fastest one of the plurality of internally generated local design clock signals, and the plurality of internally generated local design clock signals in each of the plurality of programmable logic devices that are slower than the fastest one of the plurality of internally generated local design clock signals are scheduled relative to the fastest one of the plurality of internally generated local design clock signals.