发明名称 |
Semiconductor device |
摘要 |
The present invention provides a semiconductor device that can achieve both low on-resistance and high withstand voltage, while reducing the device size, improving the manufacturing yield, and reducing the cost. The semiconductor device 1 includes a substrate 5, an epitaxial layer 6 formed on the substrate 5 and formed with a gate trench 11, a gate insulating film 17 formed on the side surface 14 and the bottom surface 15 of the gate trench 11, a gate electrode 20 embedded in the gate trench 11 and opposed to the epitaxial layer 6 with the gate insulating film 17 therebetween, and a source layer 25, a channel layer 26, and a drift layer 27 formed in this order from a first surface to a second surface of the epitaxial layer 6, in which the on-resistance Ron represented by a variable “y” and the withstand voltage Vb represented by a variable “x” functionally satisfy the following relational expression (1):
y≦9×10−7x2−0.0004x+0.7001 (1). |
申请公布号 |
US9496384(B2) |
申请公布日期 |
2016.11.15 |
申请号 |
US201214362016 |
申请日期 |
2012.11.30 |
申请人 |
ROHM CO., LTD. |
发明人 |
Nakano Yuki |
分类号 |
H01L29/78;H01L29/06;H01L29/16;H01L29/10;H01L29/423;H01L29/417;H01L29/04 |
主分类号 |
H01L29/78 |
代理机构 |
Hamre, Schumann, Mueller & Larson, P.C. |
代理人 |
Hamre, Schumann, Mueller & Larson, P.C. |
主权项 |
1. A semiconductor device comprising:
a first conductive-type SiC substrate; a first conductive-type SiC epitaxial layer formed on the substrate and having a gate trench; a gate insulating film formed on a side surface and a bottom surface of the gate trench; a gate electrode embedded in the gate trench; a first conductive-type source layer formed such that the source layer is formed on a first surface of the epitaxial layer to define a portion of the side surface of the gate trench; a second conductive-type channel layer formed such that the channel layer is in contact with the source layer to define a portion of the side surface of the gate trench; and a first conductive-type drift layer formed such that the drift layer is in contact with the channel layer to define the bottom surface of the gate trench, wherein on-resistance Ron of the semiconductor device represented by a variable “y” and withstand voltage Vb of the semiconductor device represented by a variable “x” functionally satisfy the following relational expression (4):
y≦2×10−7x2−0.0002x+0.9551 (4)wherein x≧600 and y≧0.25 in the relational expression (4). |
地址 |
Kyoto JP |