| 摘要 |
A semiconductor memory device includes a memory cell portion and at least one output part being provided with a plurality of read data DQ0Z to DQ3Z which are read from the memory cell portion and a mode selection signal TESTZ. The output part has a logic decision circuit 30 for producing a control signal indicating whether logic levels of the plurality of read data DQ0Z to DQ3Z are all the same, and an output circuit 36 controlled to operate in at least one of two states, a first state being to transmit first read data DQ0Z of the plurality of read data to an output port 37 of the output circuit 36 and a second state being to set the output port 37 to be at a high-impedance state depending on the control signal and the mode selection signal TESTZ. In the output part, when the mode selection signal indicates a normal mode, the output circuit operates in said first state, and when the mode selection signal indicates a test mode, the output circuit operates in one of said first state and said second state depending on the control signal. |
