| 摘要 |
A peak hold circuit includes an error amplification circuit having a first transistor section receiving an input voltage and a second transistor section constituting a differential error amplifier together with the first transistor section. The second transistor section has a plurality of transistors connected in parallel so as to operate individually. The peak hold circuit also includes a switching circuit having a plurality of switching transistors operated in accordance with an operation voltage of each of the transistors of the second transistor section, a charging circuit including a capacitor, for charging the capacitor stage by stage in accordance with a switching operation of each of the switching transistors of the switching circuit, and an output circuit for outputting a charging potential of the capacitor as a peak value signal of the input voltage.
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