| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To prevent that data of a low SNM memory cell is destroyed when data is written and read, also to reduce area of a memory cell by sharing a transfer gate for writing data, in a memory cell array of SRAM. <P>SOLUTION: Paths for writing are provided by connecting respectively data writing transfer gates WT1, WT2 and transistors WD1, WD2 for writing buffer to a data latch circuit storing data, these paths are controlled by a word line WL and bit lines WBL, /WBL for writing data. Also, paths for reading are provided by connecting a transistor RD1 for reading driver and a transfer gate RT1 for reading to the latch circuit, these paths are controlled by the word line WL, the bit line RBL for reading, and data of the data latch circuit. <P>COPYRIGHT: (C)2007,JPO&INPIT</p> |
