| 摘要 |
A memory device and erase verifying method of therefore is provided to reducing column scanning time at the same time by performing the erase verification of each plane. A memory cell array(210) comprises the first and second planes(211, 212), and a page buffer part(220) includes the first and second page buffer parts(221, 222). The IO controller(230) comprises the first and second IO controllers(231, 232), and the data Mux(250) includes a redundancy MUX(251), data Mux(252) and erase verification part(253). A page buffer control unit(240) outputs the control signal controlling the page buffer part and IO controller according to the column address and plane selection signal(SEL P1, SEL P2). The data Mux outputs the data of the first and the second plane and redundancy cell to the global data line, and it performs the erase verification by using data of the plane. |
