Testing a processor assembly

摘要

A testing backplane apparatus includes first test ports configured to receive a first processor assembly under test and the plurality of first test ports may be an even number of first test ports or an odd number of first test ports. The testing backplane apparatus includes second test ports, where each first test port corresponds to a second test port and the second test ports connect to a second processor assembly. The testing backplane apparatus includes a signal pathway from each first test port to a second test port. The signal pathway includes a signal path length within a range between a maximum signal path length and a minimum signal path length. Each port on the first processor assembly corresponds to each port on the second processor assembly and the testing backplane apparatus is configured differently from a backplane used as a final destination for operating the first processor assembly.

主权项

1. A testing backplane apparatus comprising:
a plurality of first test ports, the plurality first test ports configured to receive a first processor assembly, the first processor assembly comprising a target processor assembly under test, the plurality of first test ports comprising one of an even number of first test ports and an odd number of first test ports; a plurality of second test ports, wherein each first test port corresponds to a second test port, the plurality of second test ports connecting to a second processor assembly; and a signal pathway from each first test port to a second test port, the signal pathway comprising a signal path length, the signal path length within a range between a maximum signal path length and a minimum signal path length, wherein one or more of the signal pathways comprise a tunable signal pathway, the tunable signal pathway comprising one or more variable components to adjust characteristics of the tunable signal pathway in order to test the first processor assembly under various conditions, the characteristics comprising one or more of impedance and a signal pathway length, wherein each port on the first processor assembly corresponds to each port on the second processor assembly such that signals are transmitted between corresponding ports of the first processor assembly and the second processor assembly during the testing of at least one of the first processor assembly and the second processor assembly.