Mechanism for MEMS bump side wall angle improvement

摘要

The present disclosure relates to a bump processing method and/or resulting MEMS-CMOS structure, in which one or more anti-stiction bumps are formed within a substrate prior to the formation of a cavity in which the one or more anti-stiction bumps reside. By forming the one or more anti-stiction bumps prior to a cavity, the sidewall angle and the top critical dimension (i.e., surface area) of the one or more anti-stiction bumps are reduced. The reduction in sidewall angle and critical dimension reduces stiction between a substrate and a moveable part of a MEMS device. By reducing the size of the anti-stiction bumps through a processing sequence change, lithographic problems such as reduction of the lithographic processing window and bump photoresist collapse are avoided.

主权项

1. An integrated chip, comprising:
a dielectric material disposed onto a complementary metal oxide semiconductor (CMOS) substrate and having a cavity that extends through the dielectric material from a bottom surface of the cavity located within the dielectric material to a top surface of the dielectric material; one or more anti-stiction bumps disposed within the cavity and connected to the bottom surface of the cavity, wherein the one or more anti-stiction bumps have a tapered vertical sidewall angle of less than 90°, and wherein a bottom width of an anti-stiction bump is larger than a top width of the anti-stiction bump; one or more metal interconnect layers disposed within the dielectric material at positions substantially vertically disposed between the cavity and the substrate; wherein some of the dielectric material is positioned between the cavity and the CMOS substrate; and wherein the one or more anti-stiction bumps extend outward from the bottom surface of the cavity to a first distance, the one or more anti-stiction bumps are a second distance from the top surface of the dielectric material, and the first distance is smaller than the second distance.