Branch processing method and system

摘要

A method for branch processing is provided. The method includes determining an instruction type of an instruction written into a cache memory and recording the instruction type. The method also includes calculating a branch target instruction address of the branch instruction and recording target address information corresponding to the branch target instruction address when the instruction is a branch instruction, where the target address information corresponds to one instruction segment containing at least the branch target instruction. Further, the method includes filling the instruction segment containing at least the branch target instruction into the position corresponding to the target address information in the cache memory based on the branch target instruction address when the branch target instruction is not stored in the cache memory, such that before a CPU core executes the branch instruction, a next instruction following the branch instruction in a program sequence and the branch target instruction of the branch instruction are stored in the cache memory.

主权项

1. A branch processing method for controlling a pipeline operation of a processor, comprising:
determining an instruction type of an instruction written into a cache memory and recording the instruction type; when the instruction is a branch instruction, calculating a branch target instruction address of the branch instruction and recording target address information corresponding to the branch target instruction address, wherein the target address information corresponds to one instruction segment containing at least the branch target instruction; and when the branch target instruction is not stored in the cache memory, based on the branch target instruction address, filling the instruction segment containing at least the branch target instruction into the position corresponding to the target address information in the cache memory, such that, before a CPU core executes the branch instruction, a next instruction following the branch instruction in a program sequence and the branch target instruction of the branch instruction are stored in the cache memory, wherein: every instruction in the cache memory has one instruction type and one target address information corresponding to the instruction; the instruction type includes a function call instruction and a function return instruction; and when the CPU core executes the function call instruction, pushing target address information corresponding to an address returned by the function to a stack, wherein the target address information is one of the address information corresponding to the function call instruction and the address information of a next instruction following the function call instruction.