Flash memory cell structure having a high gate-coupling coefficient and a select gate

摘要

A flash memory cell structure comprising a semiconductor substrate having a first transistor and a second transistor formed thereon. The first transistor has a stacked gate and a first source/drain regions, wherein the stacked gate further includes a floating gate and a control gate. The control gate is formed above the floating gate. The second transistor is electrically connected in series with the first transistor. The second transistor functions as a select transistor and includes a gate and a second source/drain regions.