发明名称 Gapfill and planarization process for shallow trench isolation
摘要 Described is a method for filling shallow trench isolation (STI) trenches in a semiconductor substrate of an integrated circuit with an insulating material and planarizing the resulting structure to the level of adjacent portions of the integrated circuit. The method comprises forming trenches in the non-active regions of a semiconductor substrate, depositing a layer of oxide in the trenches and over the surface of the semiconductor substrate, and removing the oxide from the active areas of the integrated circuit structure, leaving oxide-filled shallow trench isolation structures having a substantially planar topography with respect to the rest of the integrated circuit structure.
申请公布号 US5851899(A) 申请公布日期 1998.12.22
申请号 US19960694072 申请日期 1996.08.08
申请人 SIEMENS AKTIENGESELLSCHAFT 发明人 WEIGAND, PETER
分类号 H01L21/76;H01L21/3105;H01L21/762;(IPC1-7):H01L21/76 主分类号 H01L21/76
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