发明名称 |
Power amplifier with an idle current trimmed and a method of trimming the power amplifier |
摘要 |
A power amplifier including an FET and a gate bias circuit having a variable resistor (VR) and a method of trimming the VR in the power amplifier are disclosed. The VR is trimmed to make the bias voltage to a pinch-off voltage of the FET. A first current in the pinch-off voltage condition from a bias supply voltage is measured. The VR is adjusted with a second current from the bias supply voltage measured. A difference between the first and second drain current values is calculated and a resistance of the VR is determined to make the difference within a reference. A second VR may be connected to the VR in parallel to make trimming the bias voltage easier or more accurately. The second VR may comprise a printed circuit pattern which shows 0 OMEGA for the pinch-off condition and the printed circuit pattern also provides the infinite resistance when it is cut to adjust the VR. Another power amplifier including a memory and a D/A converter for generating the gate bias voltage is also disclosed. The memory stores data making the FET in the pinch-off condition to measure the first current, a set of data varying the second current to adjust the VR and can store the data making the difference within the predetermined value. In the case of multi-stage, trimming is performed from one of stages of which reference is smallest.
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申请公布号 |
US5986503(A) |
申请公布日期 |
1999.11.16 |
申请号 |
US19980066778 |
申请日期 |
1998.04.27 |
申请人 |
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. |
发明人 |
ICHIKAWA, YOHEI |
分类号 |
H03F3/60;H03F1/30;H03F3/193;(IPC1-7):H03F3/16;H03F3/04 |
主分类号 |
H03F3/60 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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