Void forming method for fabricating low dielectric constant dielectric layer

摘要

A method for forming a dielectric layer within a microelectronics fabrication. There is first provided a microelectronics substrate layer employed within a microelectronics fabrication. There is then formed upon the microelectronics substrate layer a patterned microelectronics layer. There is then formed conformally over the patterned microelectronics layer a conformal silicon oxide dielectric layer formed employing a plasma enhanced chemical vapor deposition (PECVD) method employing silane as a silicon source material. The conformal silicon oxide dielectric layer comprises: (1) a first region formed over the upper surface of the patterned microelectronics layer; (2) a second region formed interposed between a series of patterns which comprises the patterned microelectronics layer and parallel with a series of sidewalls of the series of patterns which comprises the patterned microelectronics layer; and (3) a third region formed interposed between the series of patterns which comprises the patterned microelectronics layer but not parallel with the series of sidewalls of the series of patterns which comprises the patterned microelectronics layer. There is then treated with an oxygen containing plasma the conformal silicon oxide dielectric layer to enhance the rate of formation of a second silicon oxide dielectric layer upon the first region of the conformal silicon oxide dielectric layer with respect to at least the second region of the conformal silicon oxide dielectric layer. The second silicon oxide dielectric layer is formed employing an ozone assisted thermal chemical vapor deposition (CVD) method employing tetraethylorthosilicate (TEOS) as a silicon source material. Finally, there is then formed upon the oxygen containing plasma treated conformal silicon oxide dielectric layer the second silicon oxide dielectric layer, where the second silicon oxide dielectric layer defines, at least in part, a series of voids formed interposed between the series of patterns which comprises the patterned microelectronics layer.