PROCESS FOR FABRICATING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE HAVING POLYCIDE LINE AND IMPURITY REGION RESPECTIVELY EXPOSED TO CONTACT HOLES DIFFERENT IN DEPTH

摘要

When contact holes are concurrently formed in an inter-level insulating layer over an impurity region in a silicon substrate and a polycide line on a thick field oxide layer, the manufacturer interrupts the etching at the refractory metal silicide layer of the polycide line, and restarts the etching after removal of a part of the refractory metal silicide layer exposed to the short contact hole, thereby preventing the impurity region from undesirable etching for the refractory metal silicide layer.