PROCESSOR INCLUDING SINGLE INVALIDATE PAGE INSTRUCTION

摘要

A processor including a translation lookaside buffer (TLB), an instruction translator, and a memory subsystem. The TLB caches virtual to physical address translations. The instruction translator incorporates a microinstruction set for the processor that includes a single invalidate page instruction. The invalidate page instruction, when executed by the processor, causes the processor to perform a pseudo translation process in which a virtual address is submitted to the TLB to identify matching entries in the TLB that match the virtual address. The memory subsystem invalidates the matching entries in the TLB. The TLB may include a data TLB and an instruction TLB. The memory subsystem may include a tablewalk engine that performs a pseudo tablewalk to invalidate entries in the TLB and in one or more paging caches. The invalidate page instruction may specify invalidation of only those entries indicated as local.

主权项

1. A processor, comprising:
a translation lookaside buffer (TLB) that caches virtual to physical address translations; an instruction translator that incorporates a microinstruction set of a microarchitecture of the processor, wherein said microinstruction set includes a single invalidate page instruction, wherein said invalidate page instruction, when executed by the processor along with a specified virtual address, causes the processor to perform a pseudo translation process in which said virtual address is submitted to said TLB to identify matching entries in said TLB that match said virtual address; and a memory subsystem that invalidates said matching entries in said TLB.