发明名称 MRAM integration techniques for technology scaling
摘要 A magnetoresistive random-access memory (MRAM) integration compatible with shrinking device technologies includes a magnetic tunnel junction (MTJ) formed in a common interlayer metal dielectric (IMD) layer with one or more logic elements. The MTJ is connected to a bottom metal line in a bottom IMD layer and a top via connected to a top IMD layer. The MTJ substantially extends between one or more bottom cap layers configured to separate the common IMD layer and the bottom IMD layer and one or more top cap layers configured to separate the common IMD layer and the top IMD layer. The MTJ can include a top electrode to connect to the top via or be directly connected to the top via through a hard mask for smaller device technologies. The logic elements include vias, metal lines, and semiconductor devices.
申请公布号 US9406875(B2) 申请公布日期 2016.08.02
申请号 US201314109200 申请日期 2013.12.17
申请人 QUALCOMM Incorporated 发明人 Li Xia;Lu Yu;Kang Seung Hyuk
分类号 H01L29/82;H01L43/12;H01L27/22;G11C11/16;H01L43/08 主分类号 H01L29/82
代理机构 Muncy, Geissler, Olds & Lowe, P.C. 代理人 Muncy, Geissler, Olds & Lowe, P.C.
主权项 1. A magnetoresistive random-access memory (MRAM) comprising: a magnetic tunnel junction (MTJ) formed in a common interlayer metal dielectric (IMD) layer with one or more logic elements, wherein, the MTJ is connected to a bottom metal line in a bottom IMD layer and a top via connected to a top IMD layer, wherein the MTJ is in direct physical contact with the top via, wherein the MTJ extends between one or more bottom cap layers configured to separate the common IMD layer and the bottom IMD layer, and one or more top cap layers configured to separate the common IMD layer and the top IMD layer.
地址 San Diego CA US