发明名称 DROOP DETECTION AND REGULATION FOR PROCESSOR TILES
摘要 A processor system includes first and second regulators for regulating an adjusted supply voltage. The first and second regulators generate a plurality of control signals to regulate an adjusted power supply voltage and that generate a charge when a droop level falls below a droop threshold value by implementing first and second control loops. A supply adjustment block with the two regulators and control loops are provided for each processor core allowing different cores to have different regulated supply levels all based on one common supply. One regulator is a global regulator while another is a local regulator found in each of the processing tiles. Processing tiles are grouped into two groups wherein one group includes tiles that may powered down to save power. Voltage rails of the two groups are selectively connected to equalize voltage levels when both groups are powered on and operating.
申请公布号 US2016342185(A1) 申请公布日期 2016.11.24
申请号 US201514919364 申请日期 2015.10.21
申请人 ADVANCED MICRO DEVICES, INC. 发明人 Rodriguez Miguel;Kosonocky Stephen Victor
分类号 G06F1/30 主分类号 G06F1/30
代理机构 代理人
主权项 1. A processor system comprising: a plurality of processor tiles, each comprising: a supply adjustment block adapted to receive a supply voltage from an external voltage supply, the supply adjustment block comprising a plurality of selectable resistive elements for regulating an adjusted supply voltage based on said supply voltage and a first control signal;a first regulator coupled to generate a charge injection signal based upon a detected droop when a droop level of said supply voltage falls below a droop threshold value;charge selection logic configured to inject a charge to said at least one processor core when the charge injection signal is asserted wherein said charge selection logic is coupled to said supply adjustment block; andwherein said supply adjustment block is connected between said at least one processor core and at least one of said external voltage supply and circuit common or ground; and a second regulator coupled to receive a target supply voltage indication and a plurality of voltage level indications from the plurality of processor tiles, the second regulator configured to produce a second control signal based upon the target supply voltage indication and the plurality of voltage level indications wherein the charge selection logic generates the first control signal based on the second control signal.
地址 Sunnyvale CA US