发明名称 MULTIPLIER AND FILTER PROCESSING UNIT
摘要 <P>PROBLEM TO BE SOLVED: To reduce a hardware volume while maintaining calculation speed. <P>SOLUTION: A filter computing unit 10 includes partial product generation units 1-4 for generating partial products from input data and each filter coefficient according to Booth's algorithm; and an adder 51 for adding the partial products. A partial product generation unit includes partial product generators 1a, 1b and 1c; selectors 14, 15 disposed between the partial product generators 1b, 1c and the adder 51, for selecting the output of the partial product generator, so as to input it to the adder 51; and zero detectors f1, g1 for controlling the selectors 14, 15. Each filter coefficient is to produce one or more code data generated by the filter coefficient concerned to be continuously 0. The zero detectors f1, g1 respectively detect zeroes when being output by the partial product generators 1b, 1c, and the output of the partial product generator 1c is selected, so as to be inputted to the adder 51. <P>COPYRIGHT: (C)2008,JPO&INPIT
申请公布号 JP2007323567(A) 申请公布日期 2007.12.13
申请号 JP20060155862 申请日期 2006.06.05
申请人 NEC ELECTRONICS CORP 发明人 KATAYAMA YOICHI
分类号 G06F7/533;G06F7/53;H03H17/02;H04N19/42;H04N19/423;H04N19/44;H04N19/50;H04N19/513;H04N19/593;H04N19/60;H04N19/61;H04N19/80;H04N19/91 主分类号 G06F7/533
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