发明名称 MEMORY DEVICE
摘要 According to one embodiment, a memory device includes first to third interconnects, memory cells, and selectors. The first to third interconnects are provided along first to third directions, respectively. The memory cells includes variable resistance layers formed on two side surfaces, facing each other in the first direction, of the third interconnects. The selectors couple the third interconnects with the first interconnects. One of the selectors includes a semiconductor layer provided between associated one of the third interconnects and associated one of the first interconnects, and gates formed on two side surfaces of the semiconductor layer facing each other in the first direction with gate insulating films interposed therebetween.
申请公布号 US2016254320(A1) 申请公布日期 2016.09.01
申请号 US201615152342 申请日期 2016.05.11
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 MUROOKA Kenichi
分类号 H01L27/24;G11C13/00;H01L45/00;G11C5/06;H01L21/768;H01L29/66 主分类号 H01L27/24
代理机构 代理人
主权项 1. A fabricating method of a memory device comprising: forming a plurality of global bit lines in a first direction; forming a semiconductor layer on the global bit lines; patterning the semiconductor layer in a second direction orthogonal to the first direction; forming a plurality of gate insulating films on side surfaces of the patterned semiconductor layer; forming gate electrodes on the side surfaces of the patterned semiconductor layer; forming a plurality of layers of word lines on the patterned semiconductor layer; forming a variable resistance material on side surfaces of the word lines; and forming a plurality of bit lines in contact with the variable resistance material and the upper surface of the semiconductor layer.
地址 Minato-ku JP