发明名称 Thin Film Transistor and Method of Fabricating the Same, Array Substrate and Method of Fabricating the Same, and Display Device
摘要 The present invention provides a thin film transistor and a method of fabricating the same, an array substrate and a method of fabricating the same, and a display device. The thin film transistor comprises a gate, a source, a drain, a gate insulation layer, an active layer, a passivation layer, a first electrode connection line and a second electrode connection line. The gate, the source and the drain are provided in the same layer and comprise the same material. The gate insulation layer is provided above the gate, the active layer is provided above the gate insulation layer, and a pattern of the gate insulation layer, a pattern of the gate and a pattern of the active layer coincide with each other. The passivation layer covers the source, the drain and the active layer, and the passivation layer has a first via hole corresponding to a position of the source, a second via hole corresponding to a position of the drain, and a third via hole and a fourth via hole corresponding to a position of the active layer provided therein. The first electrode connection line connects the source with the active layer through the first via hole and the third via hole, and the second electrode connection line connects the drain with the active layer through the second via hole and the fourth via hole.
申请公布号 US2016254285(A1) 申请公布日期 2016.09.01
申请号 US201514768009 申请日期 2015.01.08
申请人 BOE TECHNOLOGY GROUP CO., LTD. 发明人 LONG Chunping;WANG Zuqiang
分类号 H01L27/12;H01L29/49;H01L29/786 主分类号 H01L27/12
代理机构 代理人
主权项 1. A low-temperature polysilicon thin film transistor, comprising a gate, a source, a drain, a gate insulation layer, an active layer, a passivation layer, a first electrode connection line and a second electrode connection line, wherein the gate, the source and the drain are provided in the same layer and comprise the same material; the gate insulation layer is provided on the gate, the active layer is provided on the gate insulation layer, and a pattern of the gate insulation layer, a pattern of the gate and a pattern of the active layer coincide with each other; the passivation layer covers the source, the drain and the active layer, and the passivation layer has a first via hole corresponding to a position of the source, a second via hole corresponding to a position of the drain, and a third via hole and a fourth via hole corresponding to a position of the active layer provided therein; and the first electrode connection line connects the source with the active layer through the first via hole and the third via hole, and the second electrode connection line connects the drain with the active layer through the second via hole and the fourth via hole.
地址 Beijing CN