High performance interface between an asynchronous bus and one or more processors or the like

摘要

A bus interface coupling one or more processors to a standardized bus, such as the Futurebus. The bus interface controls the assertion of all address and data handshaking signals on the bus while sending control signals to address/data transceivers coupled in between the bus and the processors. The interface comprises a plurality of synchronous state machines coupled to the processors for passing status and command data to a plurality of master and slave devices coupled to the bus. The interface also comprises a plurality of asynchronous state machines coupled between the synchronous state machines and the bus. The asynchronous machines quickly detect and assert the necessary handshaking signals of the bus protocol. The interface also controls the address/data transceivers coupled between the processors and the bus and provides an efficient throughput of data to and from the bus. Items coupled to the bus interface can operate either as slave or master devices. The bus interface handles the complex asynchronous interface with the bus and provides a much easier synchronous interface with the master and slave devices coupled to the bus.