发明名称 Reduced hardware look up table multiplier
摘要 A method and apparatus for multiplying an N bit number X(t) by an M bit number O, and a method for making such an apparatus for multiplying numbers are described. The N bit number is partitioned into K non-overlapping bit groups having priorities ranging from 0, which corresponds to the least significant bits in the value X(t), to K-1, which corresponds to the most significant bits in the value X(t). Each bit group functions as an address which accesses a first value in a respective Look Up Table (LUT). The values from the respective LUTs represent a sum of a constant, which is different for different LUTs, and the product of C and the binary value of the bit group to which the LUT corresponds. The values of the LUTs are added together, effectively bit shifted in accordance with their relative priorities, to form a partial product. The process is repeated with the remaining bit groups of X(t) in their order of priority, highest to lowest. An adder partial products until a single result is obtained. The single result is the (N+M) bit product of C and X(t). the correct result for this product is obtained from the adder tree because the individual constants added to the LUTs, which correspond to the bit groups, compensate the final result for the effects of the effective bit shifting and adding operations.
申请公布号 US5255216(A) 申请公布日期 1993.10.19
申请号 US19910746385 申请日期 1991.08.16
申请人 INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 BLANZ, WOLF-EKKEHARD;COX, CHARLES E.
分类号 G06F1/035;G06F7/52;G06F7/523;(IPC1-7):G06F7/52 主分类号 G06F1/035
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