| 摘要 |
Phase and frequency locking of a controlled signal to a reference signal is obtained in a digital phase locked loop using efficient computational procedures which are carried out rapidly with minimal computational burden on a digital processor. During each cycle of the controlled signal, the time difference between the periods and the phases of the reference signal and the controlled signal are measured. These measured variables determine the predicted changes of the period of the controlled signal to bring the controlled signal into phase and frequency lock with the reference. The change allowed in the period between each discrete cycle is constrained to be less than or equal to a selected maximum amount of time. The predicted changes of period are determined such that the direction and amount of change in period during at least the first discrete cycle is such that for subsequent changes in period, the change will be at the maximum allowed amount of time change, thereby minimizing the total time required to achieve phase and frequency lock. The next cycle of the controlled signal is then changed in accordance with the change determined in this manner, with recalculation of the predicted changes during each cycle of the controlled signal to allow tracking of changes in the reference signal. The reference signal can be AC line power provided to an uninterruptible power supply, which uses the controlled signal to control an inverter to supply AC power derived from a battery when the main AC power fails.
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