| 摘要 |
<p>The memory refresh circuitry includes two banks of memory cells (201) arranged in rows and columns. A row decoder (210a) for selects a row in one bank (201a) in response to a row address from a first group of row addresses. A second row decoder (210b) selects a row in the second bank (201b) in response to a row address from a second group of row addresses. Row address circuitry (208) presents a sequence of row addresses to the row decoders in response to a single row address received at an address port to the memory circuitry. The row address circuitry presents only row addresses of the first group in a refresh mode. Refresh circuitry (217) couples the row address circuitry with the second row decoder, and in the refresh mode converts a row address in the first group presented by the row address circuitry into a row address in the second group for use by the second row decoder. Pref. the refresh circuitry converts the address of the first group to an address of the second group by inverting a selected bit of the first group address e.g. a LSB of the address.</p> |
