发明名称 |
Communication unit and sliced radio frequency module therefor |
摘要 |
A communication unit includes at least one divider module arranged to receive a radio frequency (RF) signal and output a divided representation of the RF signal, and a plurality of sliced RF modules. Each of the plurality of sliced RF modules includes: an input for receiving a clock signal; a timing synchronization module arranged to receive the divided representation of the RF signal and synchronize the divided representation of the RF signal to the clock signal, across the plurality of sliced RF modules; and at least one logic module operably coupled to the timing synchronization module and arranged to receive the clock signal and a synchronized output from the timing synchronization module. A combiner port is arranged to couple a number of synchronized outputs from the plurality of sliced RF modules. |
申请公布号 |
US9425949(B2) |
申请公布日期 |
2016.08.23 |
申请号 |
US201414274759 |
申请日期 |
2014.05.11 |
申请人 |
MediaTek Singapore Pte. Ltd. |
发明人 |
Fong Neric;Lu Siu-Chuang Ivan;Chang Chunwei |
分类号 |
H04B1/16;H04L7/00 |
主分类号 |
H04B1/16 |
代理机构 |
|
代理人 |
Hsu Winston;Margo Scott |
主权项 |
1. A communication unit comprising:
at least one divider circuit arranged to receive a radio frequency (RF) signal and output a divided representation of the RF signal; and a plurality of sliced RF modules, with each of the plurality of sliced RF modules comprising:
an input for receiving a clock signal;a timing synchronisation circuit arranged to receive the divided representation of the RF signal and synchronise the divided representation of the RF signal to the clock signal, across the plurality of sliced RF modules; andat least one logic circuit operably coupled to the timing synchronisation circuit and arranged to receive the clock signal and a synchronised output from the timing synchronisation circuit; wherein,the synchronised output is operably coupled to a combiner port arranged to couple a number of synchronised outputs from the plurality of sliced RF modules;wherein the at least one logic circuit is operably coupled to the timing synchronisation circuit, rather than being directly connected to the at least one divider circuit, for reducing current usage in RF communications. |
地址 |
Singapore SG |