发明名称 LDMOS device with graded body doping
摘要 A laterally diffused MOS (LDMOS) device includes a substrate having a p-epi layer thereon. A p-body region is in the p-epi layer. An ndrift (NDRIFT) region is within the p-body region providing a drain extension region, and a gate dielectric layer is formed over a channel region in the p-body region adjacent to and on respective sides of a junction with the NDRIFT region, and a patterned gate electrode on the gate dielectric. A DWELL region is within the p-body region, sidewall spacers are on sidewalls of the gate electrode, a source region is within the DWELL region, and a drain region is within the NDRIFT region. The p-body region includes a portion being at least one 0.5 μm wide that has a net p-type doping level above a doping level of the p-epi layer and a net p-type doping profile gradient of at least 5/μm.
申请公布号 US9461046(B1) 申请公布日期 2016.10.04
申请号 US201514974951 申请日期 2015.12.18
申请人 TEXAS INSTRUMENTS INCORPORATED 发明人 Edwards Henry Litzmann;Todd James Robert
分类号 H01L29/66;H01L27/092;H01L29/78;H01L29/06;H01L21/8238 主分类号 H01L29/66
代理机构 代理人 Garner Jacqueline J.;Cimino Frank D.
主权项 1. A method of forming a laterally diffused metal oxide semiconductor (LDMOS) device, comprising: providing a substrate having a p-epi layer thereon; forming an ndrift (NDRIFT) region including NDRIFT ion implanting within said p-epi layer; implanting a portion of said p-epi layer lateral to said NDRIFT region including at least a first well implant comprising a p-type implant (p-type DWELL implant) to form a DWELL region; forming a p-buried layer (PBL) including a high energy implant PBL implant to add doping to said p-epi layer to form a p-body region; implanting at least one shallow pwell implant (SPW implant) into said DWELL region; Rapid Thermal Processing (RTP) to first activate together at least said PBL implant and said SPW implant; forming a gate stack including forming a gate dielectric layer over a channel region in said p-body region adjacent to and on respective sides of a junction with said NDRIFT region then a patterned gate electrode on said gate dielectric layer, forming sidewall spacers on sidewalls of said gate electrode; forming a source region within said DWELL region and a drain region within said NDRIFT region, wherein said p-body region includes a portion being at least one 0.5 μm wide that has a net p-type doping level above a doping level of said p-epi layer and a net p-type doping profile gradient of at least a factor of 5/μm.
地址 Dallas TX US