发明名称 BIT BUFFER CIRCUIT
摘要 PURPOSE:To prevent a circuit from being large by devising the circuit such that a slip takes place only at a location allowed by a frame format and the frame format is unchanged. CONSTITUTION:An address load signal generating means (36-38) generates an address load signal commanding loading of an optimum read address from an enable signal at a prescribed location. Slip discrimination means (30, 31) discriminates the presence of a slip representing missing or duplicate data based on a phase difference between output data of an expansion section and the read address. A read address generating section (32) receives a prescribed address by an address load signal from an address load signal generating means when the presence of the slip of the slip discrimination means is discriminated and generates the read address synchronously with a clock signal in the device.
申请公布号 JPH0637740(A) 申请公布日期 1994.02.10
申请号 JP19920189583 申请日期 1992.07.16
申请人 FUJITSU LTD 发明人 KUDOU SHIYOUJI
分类号 H04L7/00;H04L7/08;H04L13/08 主分类号 H04L7/00
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