| 摘要 |
A semiconductor memory apparatus able to operate at a low voltage and thus preventing an increase of the operating current during charging and discharging. NMOS transistors are connected to the power supply line and bit lines, and the gates thereof are connected to a precharge signal supply line. PMOS transistors are connected to the connection points of the bit lines and sense amplifiers and the supply line of the power supply voltage. The gates thereof are connected to the precharge signal supply line through inverters. Transfer gates are connected to the connection points of the bit lines and the NMOS transistors. The gates thereof are connected to the column switch signal supply line. Only one bit line of the selected column is precharged to the power supply voltage level. The other bit lines are held at the predetermined low potential.
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