| 摘要 |
A P component region (2) is formed of a surface silicon layer of an SOI substrate and isolated, and a gate electrode (21) is provided above the P component region (2) with a gate oxidation film (15) therebetween. A lightly doped P region (37) is formed in the P component region (2), an N source region (7) formed of a conduction type different from that of the lightly doped P region (37) and formed shallow in the P component region (2) such that a back surface thereof does not contact a buried oxidation film (19) is provided in the P component region (2), an N offset drain region (9) is provided on the opposite side thereto across the gate electrode (21), a drain region (5) is provided in the N offset drain region (9) in a manner not come into contact with the gate oxidation film (15), and a channel doped layer (25) is provided under the gate oxidation film (15).
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