| 摘要 |
<p>A method for fabricating a semiconductor memory device is provided to control variation of a threshold voltage of a memory cell by previously blocking penetration of contaminants into a gate electrode. A semiconductor substrate(110) is prepared on which a plurality of gate electrodes(117a,117b) are formed. A source/drain region(119a,119b) is formed in the substrate exposed to both sides of the gate electrode. A planarization stop layer and a planarization block layer are sequentially deposited along the step of the upper part of the substrate including the gate electrode. The planarization block layer can be made of a polysilicon layer. An interlayer dielectric(123a) is deposited on the planarization blocking layer. The interlayer dielectric and the planarization block layer are planarized in a manner that the planarization stop layer is not damaged. The interlayer dielectric can be planarized by performing a CMP process twice. The interlayer dielectric, the planarization block layer and the planarization stop layer are partially etched to expose the source/drain region so that a source/drain contact hole is formed. A source/drain contact plug is formed to bury the source/drain contact hole.</p> |
