发明名称 Metal wiring of semiconductor device and method for manufacturing the same
摘要 A metal wiring for applying a voltage to a semiconductor component of a semiconductor device, the semiconductor device comprising a low voltage applying region adjacent to a high voltage applying region, is provide. The metal wiring includes: an isolator region, a first lower metal layer electrically connected to the semiconductor component, a first upper metal layer configured to be electrically connected to an external power supply, and a plurality of inter-metal dielectric layers deposited between the first lower metal layer and the first upper metal layer, each of the plurality of inter-metal dielectric layers comprising at least one contact plug for providing an electrical connection between the first lower metal layer and the first upper metal layer.
申请公布号 US9362207(B2) 申请公布日期 2016.06.07
申请号 US201213714866 申请日期 2012.12.14
申请人 Magnachip Semiconductor, Ltd. 发明人 Kim Kwan-soo;Lee Tae-jong;Shin Kang-sup;Kim Si-bum;Kang Yang-beom;Jeong Jong-yeul
分类号 H01L23/485;H01L21/768;H01L23/522;H01L23/528;H01L23/532 主分类号 H01L23/485
代理机构 NSIP Law 代理人 NSIP Law
主权项 1. A metal wiring for applying a voltage to a semiconductor component of a semiconductor device, the semiconductor device comprising a low voltage applying region adjacent to a high voltage applying region, the metal wiring comprising: an isolator region; a first lower metal layer electrically connected to the semiconductor component; a first upper metal layer configured to be electrically connected to an external power supply; a plurality of inter-metal dielectric layers deposited between the first lower metal layer and the first upper metal layer, each of the plurality of inter-metal dielectric layers comprising at least one contact plug formed in a via trench for providing an electrical connection between the first lower metal layer and the first upper metal layer; and a plurality of etching stop layers deposited on each of the plurality of inter-metal dielectric layers, wherein the plurality of inter-metal dielectric layers are each a continuous multilayer oxide film formed between adjacent etching stop layers or between the first upper or lower metal layer and its respective adjacent etching stop layer, wherein the plurality of inter-metal dielectric layers are each a multilayer oxide film comprising a plurality of alternating tensile stress oxide layers and compressive stress oxide layers.
地址 Cheongju-si KR