Methods and devices for determining logical to physical mapping on an integrated circuit

摘要

Methods and devices for mapping logical addresses to physical locations on an integrated circuit die are disclosed herein. An embodiment of the method includes fabricating a die, where the die has a plurality of bits that are electrically accessible by way of logical addresses. A plurality of bits have known defects that form a predetermined fault pattern at a predetermined location on the die. The bits are tested by using the logical addresses, wherein the testing yields data as to the functionality of the bits. The test results are searched for the predetermined fault pattern. The physical locations of the defective bits constituting the predetermined fault pattern are correlated with their logical addresses based on the location of the predetermined fault pattern.

主权项

1. A method for mapping logical addresses to physical locations on an integrated circuit die, the method comprising:
fabricating a die, the die having a plurality of bits that are electrically accessible by way of logical addresses, wherein a plurality of bits have known defects, and wherein the plurality of bits form a predetermined fault pattern at a predetermined location on the die; testing the bits by using the logical addresses, wherein the testing yields data as to the functionality of the bits; searching the data for the predetermined fault pattern; and correlating the physical locations of the defective bits constituting the predetermined fault pattern with their logical addresses based on the location of the predetermined fault pattern.