Synchronous dynamic memory device capable of operating over wide range of operation frequencies

摘要

In a synchronous DRAM, internal clock signals in synchronism with clock signals fed from an external unit are generated by a PLL circuit or a DLL circuit to eliminate signal delays. In order to provide a dynamic RAM that is capable of stably operating with clock signals over a wide range of frequencies; a change-over circuit is provided which changes the range of variable frequencies of the PLL circuit or changes the variable delay time of the DLL circuit based upon mode-setting information fed from an external unit.