发明名称 |
LAYOUT OF METAL LINE IN MEMORY CELL |
摘要 |
PROBLEM TO BE SOLVED: To provide the layout of the metallic lines of a memory cell for simultaneously removing various constraints relating to the design of a memory cell. SOLUTION: This memory cell is provided with a polysilicon gate 2 running in a first direction. A sequence of layers of metallic lines includes a layer of bit lines 4 running in a second direction substantially orthogonal to the first direction followed by data lines 6 running in the second direction, and then word lines 8 running in the first direction. The data lines 6 are precharged to a value stored while the bit lines 4 are being used to sense data values stored in the memory cell. COPYRIGHT: (C)2008,JPO&INPIT |
申请公布号 |
JP2007324571(A) |
申请公布日期 |
2007.12.13 |
申请号 |
JP20070097692 |
申请日期 |
2007.04.03 |
申请人 |
ARM LTD |
发明人 |
WANG KARL LIN;GAJJEWAR HEMANGI UMAKANT |
分类号 |
H01L27/10;G11C11/41;H01L21/8244;H01L21/8246;H01L27/11;H01L27/112 |
主分类号 |
H01L27/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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