Processor and processing method

摘要

In a processor that includes a plurality of multipliers and a plurality of adders to execute matrix product processing, each data of input vector data involved in the arithmetic processing is used in two multipliers, whereby arithmetic processing of elements in different rows and different columns in a matrix product operation is executed with a single instruction, that enables the sharing of input data to reduce the number of times data are moved in the whole matrix product processing and reduce power consumption.

主权项

1. A processor comprising:
a processing control unit that reads four pieces of input data of a first set and four pieces of input data of a second set from a data storage unit respectively, and supplies, to a plurality of multipliers in parallel, the four pieces of input data of the first set and the four pieces of input data of the second set read from the data storage unit; a first multiplier that receives first input data of the first set at a first input and receives first input data of the second set at a second input, and outputs a product of the both input data; a second multiplier that receives second input data of the first set at a first input and receives third input data of the second set at a second input, and outputs a product of the both input data; a third multiplier that receives the second input data of the first set at a first input and receives fourth input data of the second set at a second input, and outputs a product of the both input data; a fourth multiplier that receives the first input data of the first set at a first input and receives second input data of the second set at a second input, and outputs a product of the both input data; a fifth multiplier that receives third input data of the first set at a first input and receives the first input data of the second set at a second input, and outputs a product of the both input data; a sixth multiplier that receives fourth input data of the first set at a first input and receives the third input data of the second set at a second input, and outputs a product of the both input data; a seventh multiplier that receives the fourth input data of the first set at a first input and receives the fourth input data of the second set at a second input, and outputs a product of the both input data; an eighth multiplier that receives the third input data of the first set at a first input and receives the second input data of the second set at a second input, and outputs a product of the both input data; a first adder that adds an output of the first multiplier and an output of the second multiplier to output an addition result as first output data; a second adder that adds an output of the third multiplier and an output of the fourth multiplier to output an addition result as second output data; a third adder that adds an output of the fifth multiplier and an output of the sixth multiplier to output an addition result as third output data; and a fourth adder that adds an output of the seventh multiplier and an output of the eighth multiplier to output an addition result as fourth output data.