Apparatus and methods for partitioning an integrated circuit design into multiple programmable devices

摘要

Methods and systems for partitioning a design across a plurality of programmable logic devices such as Field Programmable Gate Arrays (FPGAs) are provided. The systems include SerDes (SERializer DESerializer) interfaces, such as PCIe, (Peripheral Component Interconnect Express) in the programmable logic devices operably connecting logic blocks of the design. Embodiments include a bridge in each programmable logic device for providing synchronization and deterministic latency of packets sent between the programmable devices.

主权项

1. A method for partitioning a circuit, comprising:
employing a hardware processor for performing at least one of:
partitioning a circuit to comprise a first programmable device having a first SerDes (serializer/deserializer) and a second programmable device having a second SerDes;operably connecting the first SerDes and the second SerDes;sending a plurality of packets having a respective plurality of timestamps from the first SerDes;receiving the plurality of packets by the second SerDes;determining a respective plurality of flight times of the plurality of packets from the respective plurality of timestamps;delaying a release of a packet received by the second SerDes based on the plurality of flight times for synchronizing the release of the packet;determining a maximum flight time and a minimum flight time from the respective plurality of flight times; anddetermining a maximum frequency of a clock as a function of the maximum flight time and the minimum flight time.