Frame buffer power management

摘要

For frame buffer power management, a frame buffer includes a write circuit and a read circuit, and drives a display. A power management module terminates power to the frame buffer in response to a power reduction policy being satisfied.

主权项

1. An apparatus comprising:
a frame buffer comprising a write circuit, magnetic random-access memory (MRAM) cells, and a read circuit and that drive a display, wherein the write circuit writes pixel values to the MRAM cells and the read circuit reads the pixel values from the MRAM cells; and a power management module of semiconductor gates that terminates power to the write circuit and maintains power to the read circuit in response to a power reduction policy being satisfied, wherein the power reduction policy is satisfied in response to a last graphics input interval exceeding an input interval threshold and the last graphics input interval is a time interval from a no-pixel update signal.