| 发明名称 | Latch circuit | ||
| 摘要 | A latch circuit includes a first PMOS transistor suitable for pull-up driving a second node based on a voltage of a first node, a first NMOS transistor suitable for pull-down driving the second node based on a voltage of the first node, a second PMOS transistor suitable for pull-up driving the first node based on a voltage of the second node, a second NMOS transistor suitable for pull-down driving the first node based on a voltage of the second node, a first separation element suitable for electrically separating the first NMOS transistor from the second node when the first PMOS transistor is turned on, and a second separation element suitable for electrically separating the second NMOS transistor from the first node when the second PMOS transistor is turned on. | ||
| 申请公布号 | US9397642(B2) | 申请公布日期 | 2016.07.19 |
| 申请号 | US201514678704 | 申请日期 | 2015.04.03 |
| 申请人 | SK Hynix Inc. | 发明人 | Choi Hae-Rang;Hwang Mi-Hyun |
| 分类号 | H03K3/356 | 主分类号 | H03K3/356 |
| 代理机构 | IP & T Group LLP | 代理人 | IP & T Group LLP |
| 主权项 | 1. A latch circuit comprising: a first PMOS transistor suitable for pull-up driving a second node based on a voltage of a first node; a first NMOS transistor suitable for pull-down driving the second node based on a voltage of the first node; a second PMOS transistor suitable for pull-up driving the first node based on a voltage of the second node; a second NMOS transistor suitable for pull-down driving the first node based on a voltage of the second node; a first separation element suitable for electrically separating the first NMOS transistor from the second node when the first PMOS transistor is turned on; and a second separation element suitable for electrically separating the second NMOS transistor from the first node when the second PMOS transistor is turned on, wherein the first separation element and the second separation element include a PMOS transistor, respectively. | ||
| 地址 | Gyeonggi-do KR | ||