发明名称 |
Fold over emitter and collector field emission transistor |
摘要 |
A field emission transistor includes a gate, a fold over emitter, and fold over collector. The emitter and the collector are separated from the gate by a void and are separated from a gate contact by gate contact dielectric. The void may be a vacuum, ambient air, or a gas. Respective ends of the emitter and the collector are separated by a gap. Electrons are drawn across gap from the emitter to the collector by an electrostatic field created when a voltage is applied to the gate. The emitter and collector include a first conductive portion substantially parallel with gate and a second conductive portion substantially perpendicular with gate. The second conductive portion may be formed by bending a segment of the first conductive portion. The second conductive portion is folded inward from the first conductive portion towards the gate. Respective second conductive portions are generally aligned. |
申请公布号 |
US9431205(B1) |
申请公布日期 |
2016.08.30 |
申请号 |
US201514684762 |
申请日期 |
2015.04.13 |
申请人 |
International Business Machines Corporation |
发明人 |
Briggs Benjamin D.;Clevenger Lawrence A.;Rizzolo Michael |
分类号 |
H01L21/00;H01J21/10;H01J19/24;H01J9/02 |
主分类号 |
H01L21/00 |
代理机构 |
|
代理人 |
Zehrer Matthew C. |
主权项 |
1. A semiconductor device fabrication method compromising:
forming a dielectric layer upon a backside carrier; forming a field emission transistor trench within the dielectric layer; forming a conductive layer upon the field emission trench walls; filling the field emission trench with a gate contact dielectric; recessing the dielectric layer and the gate contact dielectric to expose a paired emitter portion and collector portion of the conductive layer; folding the exposed conductive layer paired portions inward; forming a self-aligned gate between the paired folded conductive layer portions; planarizing a backside of the dielectric layer to expose the gate contact dielectric; forming one or more backside dielectric layers upon the backside of the dielectric layer and upon the exposed gate contact dielectric; forming a gate contact trench within the one or more backside dielectric layers and within the gate contact dielectric to expose the gate, and; forming a gate contact within the gate contact trench. |
地址 |
Armonk NY US |