发明名称 Apparatus and methods for high voltage variable capacitor arrays with feed-forward capacitors
摘要 Apparatus and methods for high voltage variable capacitors are provided herein. In certain configurations, an integrated circuit (IC) includes a variable capacitor array and a bias voltage generation circuit that biases the variable capacitor array to control the array's capacitance. The variable capacitor array includes a plurality of variable capacitor cells electrically connected in parallel between a radio frequency (RF) input and an RF output of the IC. Additionally, each of the variable capacitor cells can include a cascade of two or more pairs of anti-series metal oxide semiconductor (MOS) capacitors between the RF input and the RF output. The pairs of anti-series MOS capacitors include a first MOS capacitor and a second MOS capacitor electrically connected in anti-series. The bias voltage generation circuit generates bias voltages for biasing the MOS capacitors of the variable capacitor cells.
申请公布号 US9461609(B2) 申请公布日期 2016.10.04
申请号 US201514705386 申请日期 2015.05.06
申请人 TDK Corporation 发明人 Madan Anuj;Gupta Dev V.;Lai Zhiguo
分类号 H03H7/01;H03H11/04;H03H11/28;H01L27/08;H03H1/00 主分类号 H03H7/01
代理机构 Nixon Peabody LLP 代理人 Nixon Peabody LLP
主权项 1. An integrated circuit comprising: a variable capacitor array including a plurality of variable capacitor cells electrically connected in parallel between a radio frequency (RF) input and an RF output, each of the plurality of variable capacitor cells having a capacitance configured to be controlled independently of another of the plurality of variable capacitor cells, wherein a first variable capacitor cell of the plurality of variable capacitor cells includes: two or more pairs of anti-series metal oxide semiconductor (MOS) capacitors electrically connected in series between the RF input and the RF output, wherein a first pair of the two or more pairs of anti-series MOS capacitors includes a first MOS capacitor and a second MOS capacitor electrically connected in anti-series and electrically connected to one another at a first intermediate node, and wherein a second pair of the two or more pairs of anti-series MOS capacitors includes a third MOS capacitor and a fourth MOS capacitor electrically connected in anti-series and electrically connected to one another at a second intermediate node; anda first feed-forward capacitor electrically connected between the RF input and the first intermediate node to provide a feed-forward path from the RF input to the first intermediate node.
地址 Tokyo JP