发明名称 |
Digital-to-analog converter with integrated fir filter |
摘要 |
A Digital-to-Analog Converter contains a digital shift register and a digital multiplexer. During each input signal clock period, the Digital-to-Analog Converter is multiplexed in time to perform multiple conversions on samples stored in the shift register. In this way, a weighted average of several signal samples is calculated, which corresponds to a FIR filter operation. Errors due! to Quantization Noise, INL or DNL undergo the same FIR filter characteristic. |
申请公布号 |
US9484943(B2) |
申请公布日期 |
2016.11.01 |
申请号 |
US201214345518 |
申请日期 |
2012.09.11 |
申请人 |
Op 'T Eynde Frank |
发明人 |
Op 'T Eynde Frank |
分类号 |
H03M7/00;H03M1/06;H03M3/00;H03M1/66 |
主分类号 |
H03M7/00 |
代理机构 |
The Marbury Law Group, PLLC |
代理人 |
The Marbury Law Group, PLLC |
主权项 |
1. An apparatus for performing digital-to-analog conversion of a digital input signal, comprising:
a first digital signal input to which the digital input signal is applied; a first clock signal line for providing a first clock frequency signal; a digital memory coupled to the first digital signal input and to the first clock signal line, wherein the digital memory comprises a plurality of digital memory units operable to store samples of the digital input signal and arranged in series, wherein, at a trigger of the first clock frequency signal, a new sample of the digital input signal is stored in a first of the plurality of digital memory units and at a subsequent trigger of the first clock frequency signal, the sample is transferred to a consecutive one of the plurality of digital memory units; a digital multiplexer comprising:
a plurality of multiplexer inputs coupled to each one of the plurality of digital memory units; anda multiplexer output, wherein the digital multiplexer is configured for providing at the multiplexer output one of the multiplexer inputs at a time; and a digital-to-analog converter comprising a second digital signal input coupled to the digital multiplexer output, wherein the converter and the multiplexer are configured to operate at a second speed which is an integer multiple of the first clock frequency signal, wherein the digital memory and the digital multiplexer are configured for construing a second digital signal from the samples of the digital input signal stored in the digital memory, wherein the second digital signal comprises multiple identical occurrences of each of the samples of the digital input signal, and wherein the second digital signal is applied to the second digital signal input and is configured for being converted by the digital-to-analog converter. |
地址 |
Wilsele BE |