| 摘要 |
PURPOSE: A frequency offset based lock detector and a PLL(Phase Locked Loop) circuit thereof are provided to decrease a malfunction rate due to a process variation by simply forming the circuit with a simple algorithm. CONSTITUTION: A frequency estimator(200) supplies a first detection signal activated according to the frequency difference of a feedback signal and a reference signal. A phase detector(300) is operated in the active state of the first detection signal based on the reference signal, the feedback signal and the first detection signal. The phase detector supplies the second detection signal activated according to the phase difference of the feedback signal and the reference signal. A output unit(110) supplies a lock signal activated in the simultaneous active state of the second detection signal and the first detection signal. |
