Incremental programming pulse optimization to reduce write errors

摘要

In a data storage system having multi-level memory cells, a counter tracks the number of program/erase cycles, anticipated read cycles, or anticipated length of data retention of a cell. When a threshold number of cycles is reached or length of retention or read frequency are anticipated, the cell is programmed using more program voltage pulses, narrower program voltage pulses or some other modification to the incremental step programming pulse to reduce the range where the intermediate least significant (lower) bit read voltage may be erroneous, thereby reducing the probability of write errors when the most significant page (upper) is programmed.

主权项

1. A data storage system comprising:
a processor; memory connected to the processor, the memory comprising a plurality of multi-level memory cells; a data storage element connected to the processor; and computer executable program code configured to execute on the processor, wherein the computer executable program code is configured to:
identify a first multi-level cell in the plurality of multi-level cells as being prone to write errors;modify an incremental step programming pulse via applying more pulses to shift a mean voltage distribution associated with a least significant bit; andapply the modified incremental step programming pulse to the first multi-level memory cell.