VARIABLE RESISTANCE MEMORY DEVICE AND MANUFACTURING METHOD THEREOF

摘要

A resistance variable memory has a memory cell area, a plurality of first wires arranged at intervals in a first direction in the memory cell area and arranged at intervals in a laminating direction, a plurality of second wires arranged at intervals in a second direction in the memory cell area and alternatively arranged with the first wires in a laminating direction, memory cells arranged at each crossing point between the first wire and the second wire in the memory cell area and include variable resistance elements, a first wire interconnecting area arranged separately from the memory cell area and in which conductive layers electrically conducting with the plurality of first wires are arranged, and a second wire interconnecting area arranged separately from the memory cell area and the first wire interconnecting area and in which conductive layers electrically conducting with the plurality of second wires are arranged.

主权项

1. A resistance variable memory, comprising:
a memory cell area arranged on a substrate; a plurality of first wires arranged at intervals in a first direction in the memory cell area and arranged at intervals in a laminating direction; a plurality of second wires arranged at intervals in a second direction in the memory cell area and alternatively arranged with the first wires in a laminating direction; memory cells which are arranged at each crossing point between the first wire and the second wire in the memory cell area and include variable resistance elements; a first wire interconnecting area arranged separately from the memory cell area on the substrate and in which conductive layers electrically conducting with the plurality of first wires are arranged; and a second wire interconnecting area arranged separately from the memory cell area on the substrate and the first wire interconnecting area and in which conductive layers electrically conducting with the plurality of second wires are arranged, wherein the first wire interconnecting area comprises the plurality of first wire interconnecting portions electrically conducting with each of the plurality of first wires, and wherein each of the plurality of first wire interconnecting portions comprises a first laminated body including a first conductive portion electrically conducting with a corresponding first wire, and a second conductive portions including conductive layers for a total number of the second wires and the first wires arranged on the substrate side from the corresponding first wire.