| 发明名称 | Method of operating a voltage regulator to reduce contention current | ||
| 摘要 | A method of operating a first voltage regulator includes electrically coupling a transistor of an output stage of the first voltage regulator between a first power voltage and a second power voltage, and reverse biasing a bulk of the transistor by a back-bias circuit during a standby mode of a memory array. The first voltage regulator is coupled to a second voltage regulator and reverse biasing the bulk of the transistor reduces a contention current between the first voltage regulator and the second voltage regulator. | ||
| 申请公布号 | US9502098(B2) | 申请公布日期 | 2016.11.22 |
| 申请号 | US201615014119 | 申请日期 | 2016.02.03 |
| 申请人 | TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. | 发明人 | Huang Ming-Chieh;Chern Chan-Hong;Yang Tien Chun;Lin Chih-Chang;Swei Yuwen |
| 分类号 | G11C11/24;G11C5/14;G11C8/00;G11C11/4074 | 主分类号 | G11C11/24 |
| 代理机构 | Hauptman Ham, LLP | 代理人 | Hauptman Ham, LLP |
| 主权项 | 1. A method of operating a first voltage regulator, the method comprising: electrically coupling a transistor of an output stage of the first voltage regulator between a first power voltage and a second power voltage; and reverse biasing a bulk of the transistor by a back-bias circuit during a standby mode of a memory array, wherein the first voltage regulator is coupled to a second voltage regulator and reverse biasing the bulk of the transistor reduces a contention current between the first voltage regulator and the second voltage regulator. | ||
| 地址 | TW | ||